Serial Peripheral Interface Using Vhdl

Posted : adminOn 11/17/2017

VHDL SPI Receiver. Created on 6 March 2. A SPI receiver is written in VHDL and implemented on a CPLD as a SPI slave device. This allows the CPLD to act as an output expander, turning two SPI lines and a chip select line into eight output lines 8 digital outputs. SPI Serial Peripheral Interface is a four wire synchronous serial bus. In this example, only three wires are used data, clock and chip select as data is only being received by the VHDL SPI receiver from a microcontroller the micro is the SPI master. This is the first example of microcontroller to CPLD interfacing on this VHDL course so far. The microcontroller was previously only used to generate a clock pulse for the CPLD. Spi Serial Peripheral InterfaceThis video shows the hardware, microcontroller software and VHDL code for this tutorial in action Hardware. All the hardware is in place if using the home built Xilinx CPLD board. Microcontroller. The ATtiny. Xilinx CPLD board is used to send data over the SPI lines. The ATtiny. 23. 13 has a USI Universal Serial Interface that is used to implement the SPI port. The USI does not have a chip select line usually called slave select SS on SPI, so this is implemented by using a spare microcontroller pin. If you are using a different CPLD or FPGA board, then hook up an ATtiny. If you want to use a different microcontroller or a separate microcontroller board, then you will need to write the SPI software for it yourself. Interface. The circuit diagram for the home built Xilinx CPLD board shows the connections between the ATtiny. CPLD. The diagram below shows just the SPI connections for transmitting from the microcontroller to CPLD AVR ATtiny. CPLD XC9. 53. 6XL SPI Transmit Connections. All the lines shown in the diagram are outputs from the microcontroller. Timing Diagram. The timing diagram for the SPI signals transmit only generated by the ATtiny. AVR microcontroller are shown below. Serial Peripheral Interface Specification' title='Serial Peripheral Interface Specification' />SPI Timing Diagram Transmit Only. The SPI clock phase and polarity can usually be configured in software for the microcontroller that has a SPI peripheral. The timing diagram above shows how SPI is configured in software in the ATtiny. All serial data is valid on the rising edge of the clock USCK. Microcontroller SPI Software. To generate the above SPI outputs from the ATtiny. C program, or download the Atmel Studio 6 project files which includes the source and hex files. SPItxunsigned char. Delayvoid. enable the DO and USCK pins as outputs in the DDRB register. DDRB 1 lt lt PB6 1 lt lt PB7. DDRB 1 lt lt PB4 PB4 as chip select line CS. PORTB 1 lt lt PB4 make CS line inactive high. SPItx0x. 55. Delay. Serial Peripheral Interface Master in Altera MAX Series 2014. AN485 Subscribe Send Feedback The serial peripheral interface SPI is a 4wire, serial. Design of I2C BUS Controller using VHDL 1Spandana Sunku. Serial peripheral interface, and Micro wire for interfacing high speed and low speed peripherals. The Easiest Way To Learn VHDL. The Easiest Way To Learn VHDL. Skip to main content. Toggle navigation. SurfVHDL. Home. Serial Peripheral Interface Introduction. Modeling of ADS 5547 using VHDL Serial interface mode Ammar Armghan1, Arslan Haider2, Fawad Naseer3. The Serial Peripheral Interface Bus or SPI bus is a. SPItx0x. F0. Delay. SPItx0x. C0. Delay. SPItx0x. C3. Delay. SPItxunsigned char databyte. USIDR databyte data to send. USI counter overflow flag and USI counter value. USISR 1 lt lt USIOIF. Design And Implementation Of Serial Peripheral Interface Using VhdlPORTB 1 lt lt PB4 enable CS low. USISR 1 lt lt USIOIF wait for counter to overflow. USI in 3 wire mode, pos. SW clock strobe. USICR 1 lt lt USIWM0 1 lt lt USICS1 1 lt lt USICLK 1 lt lt USITC. PORTB 1 lt lt PB4 disable CS high. Delayvoid. volatile unsigned int del 4. This program must be loaded to the ATtiny. The program sends out four bytes continuously 0x. F0, 0x. C0 and 0x. C3, each with a different value, over the SPI port. The idea is for the SPI receiver implemented on the CPLD to receive each byte from the SPI lines and display it on eight LEDs. Thinking Through the VHDL Design. Clock Pulse and Data. In this VHDL CPLD course, we have already seen how to run VHDL code when a clock edge occurs by using a VHDL process. It should not be too difficult to sample the data line on every clock pulse rising edge. Eight clock pulses are sent from the SPI master the microcontroller for every byte of data sent. Valid data can be found on the SPI data line DO data out from the microcontroller on every rising clock edge. To store the received byte, each bit can be shifted into a register on each rising edge of the clock pulse we have already seen how to shift in VHDL. Synchronization. It would be difficult to make sure that the microcontroller and CPLD stay in sync if just a clock and data line were used. Any pulse on the clock line during power up could immediately put the microcontroller and CPLD out of sync the CPLD would not know if it was the first data bit of a byte or any other bit in the byte when the microcontroller starts sending data. The chip select CS usually called slave select SS in SPI devices keeps the microcontroller and CPLD synchronized. On the falling edge of CS, we know that a new byte will be coming from the microcontroller. On the rising edge of CS, we know that we have received a byte from the microcontroller. Data Buffering. If the register used for shifting in the serial data were connected directly to the LEDs, the LEDs would all appear to be on unless a byte with a value of zero were sent. This is because we would be seeing the data being shifted at full speed across all the LEDs. The received data byte needs to be buffered in order to prevent shifting data being displayed on the LEDs. The LEDs can then be connected to the buffer register. The buffer register can then be connected to the LEDs and updated only on the rising edge of CS when the new byte of data has been fully received. VHDL SPI Receiver Code. Two VHDL code examples SPIrx. SPIrx. 3 are shown below and each explained in turn SPI Receiver VHDL Code Example 1. The first VHDL code example SPIrx. IEEE. STDLOGIC1. ALL. SPIrx. Port SCK in STDLOGIC SPI input clock. DATA in STDLOGIC SPI serial data input. CS in STDLOGIC chip select input active low. LED inout STDLOGICVECTOR 7 downto 0. SPIrx. 2top. architecture Behavioral of SPIrx. STDLOGICVECTOR 7 downto 0. SCK. if SCKevent and SCK 1 then rising edge of SCK. CS 0 then SPI CS must be selected. SCK, MSB first. datreg lt datreg6 downto 0 DATA. LEDs when not shifting CS inactive. LED lt datreg when CS 1 else LED. Behavioral. Getting the Data Bits. The VHDL process in the above code gets a data bit on every rising edge of the SPI clock. A data bit will only be read if the CS line is active low to prevent any spurious signals on the clock line causing the microcontroller and CPLD to get out of sync. Shifting the Data into a Register. The data bits that occur at each rising edge of the clock pulse are shifted into the datreg register using the following line of VHDL code. DATA. The shifting operation is done by moving the bottom 7 bits 6 down to 0 left by one bit in the datreg register. At the same time the valid data on the DATA line is appended to the seven lower bits that are being shifted. The bit from the DATA line is appended by using the VHDL concatenation operator. This effectively shifts the bottom seven bits of datreg left by one and puts the new data bit from the DATA line into bit 0 of datreg. Displaying the Data Bytes. The received data bytes are displayed on the LEDs by updating a received byte only when the CS line is inactive high by using the VHDL when else construct. LED lt datreg when CS 1 else LED. In the entity part of the VHDL code, LED was made inout so that it can be read back in the above line of code after the else. How to Design SPI Controller in VHDLSerial Peripheral Interface Introduction. The Serial Peripheral Interface SPI bus is a synchronous serial communication controller specification used for short distance communication, primarily in embedded systems. The interface was developed by Motorola and has become a de facto standard. Typical applications include sensors, Secure Digital cards, and liquid crystal displays. SPI devices communicate in full duplex mode using a master slave architecture with a single master. The SPI master device originates the frame for reading and writing. Multiple SPI slave devices are supported through selection with individual slave select SS lines as in Figure 2. Figure 1 SPI Master single slave The SPI is a four wire serial bus as you can see in Figure 1 and in Figure 2. Figure 2 SPI Master three slaves For further information see the Wikipedia Page dedicated to the SPI. SPI controller architecture overview. The SPI bus specifies four logic signals SCLK Serial Clock output from master. MOSI Master Output, Slave Input output from master. MISO Master Input, Slave Output output from slave. SS Slave Select active low, output from master. You can find alternate naming, but the functionalities are the same. SPI timing example is shown in Figure 4. The MOSI can be clocked either on rising or falling edge of SCKL. Cdr Dicom For Windows. If MISO change on rising edge of SCLK, MISO will change on falling and vice versa. Figure 4 SPI timing Data transmission begins on the falling edge of SS, then a number N of clock cycles will be provided. The MOSI is driven with the output data payload. The data payload can contain either data and command. If MOSI contains a command, i. SCLK cycle, MISO will be driven with the serial data value read from the slave. SPI controller VHDL implementation. Before writing the SPI controller VHDL code, lets review the SPI controller architecture of Figure 5. Figure 5 SPI Controller interface iclk              input clock. Figure 6 SPI Controller FSM The SPI controller VHDL code will implement the FSM described in Figure 6. The input parallel data will be send using txstart input signal. The FSM goes to STTXRX state for a programmed number of clock cycles. During the data transmission, MISO input is sampled on the internal shift register. At the end of data transmission, the parallelized input is available on oparalleldata output port and a pulse is generated on otxend port. A possible VHDL implementation of SPI controller is available below library ieee. N integer 8 number of bit to serialize. CLKDIV integer 1. CLKDIV. iclk in stdlogic. TX on serial line. TX data completed odataparallel available. N 1 downto 0 data to sent. N 1 downto 0 received data. STRESET. STTXRX. STEND. CLKDIV2. N. signal wtccounterdata stdlogic. TX on serial line. N 1 downto 0 data to sent. N 1 downto 0 received data. STRESET. elsifrisingedgeiclk then. STTXRX. if wtccounterdata1 and rsclkrise1 then wstnext lt STEND. STTXRX. when STEND. STRESET. wstnext lt STEND. STRESET. ifrtxstart1 then wstnext lt STTXRX. STRESET. end process pcomb. N 1. rcounterclockena lt 0. STTXRX. N 2 downto 0 imiso. N 1. rtxdata lt rtxdataN 2 downto 0 1. STEND. otxend lt rsclkfall. N 1. rcounterclockena lt 1. STRESET. rtxdata lt idataparallel. N 1. rcounterclockena lt 0. CLKDIV 1 then firse edge fall. CLKDIV 1 then. In the following figures, there are three examples of SPI protocol simulation. In the Modelsim windows is clear the SPI protocol behavior input parallel data is serialized on MOSI output port. The MISO input data is parallelized in the oparalleldata port of the SPI controller. Figure 7 shows an overall simulation view of three SPI cycles. Figure 7 SPI Controller Modelsi simulation All view Figure 8 shows a zoom on the second SPI cycle. Figure 8 SPI Controller Modelsim simulation zoom one cycle Figure 9 shows a zoom on the SPI cycle start. The system clock is set to 1. The SCLK is generated dividing by 2. CLKDIVFigure 9 SPI Controller Modelsim simulation cycle start The SPI controller VHDL code above is technology independent and can be implemented either on FPGA or ASIC. Figure 1. 0 shows Altera Quartus II RTL viewer of the SPI VHDL code implementation above. Figure 1. 0 SPI Controller Quartus II RTL viewer The SPI controller VHDL code has been tested on Altera Cyclone III FPGA with 8 bit serial and parallel data. The implementation takes 5. Logic Element LE and performs 4. MHz as reported in the Quartus II area report and timing report below. Figure 1. 1 SPI Controller Altera Quartus II Area report for Cyclone III Figure 1. SPI Controller Altera Quartus II Timing report for Cyclone III References https en. SerialPeripheralInterfaceBus. If you appreciated this post, please help us to share it with your friend. If you need to contact us, please write to surf. We appreciate any of your comment, please post below.